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compact, 800 ma, 3 mhz, step-down dc-to-dc converter adp2138/adp2139 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features input voltage: 2.3 v to 5.5 v peak efficiency: 95% 3 mhz fixed frequency operation typical quiescent current: 24 a very small solution size 6-lead, 1 mm 1.5 mm wlcsp package fast load and line transient response 100% duty cycle low dropout mode internal synchronous rectifier, compensation, and soft start current overload and thermal shutdown protections ultralow shutdown current: 0.2 a (typical) forced pwm and automatic pwm/psm modes applications pdas and palmtop computers wireless handsets digital audio, portable media players digital cameras, gps navigation units general description the adp2138 and adp2139 are high efficiency, low quiescent current, synchronous step-down dc-to-dc converters. the adp2139 has the additional feature of an internal discharge switch. the total solution requires only three tiny external components. when the mode pin is set high, the buck regulator operates in forced pwm mode, which provides low peak-to-peak ripple for power supply noise sensitive loads at the expense of light load efficiency. when the mode pin is set low, the buck regulator automatically switches operating modes, depending on the load current level. at higher output loads, the buck regulator operates in pwm mode. when the load current falls below a predefined threshold, the regulator operates in power save mode (psm), improving light load efficiency. the adp2138/adp2139 operate on input voltages of 2.3 v to 5.5 v, which allows for single lithium or lithium polymer cell, multiple alkaline or nimh cell, pcmcia, usb, and other standard power sources. the maximum load current of 800 ma is achievable across the input voltage range. the adp2138/adp2139 are available in fixed output voltages of 3.3 v, 3.0 v, 2.8 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, 1.0 v, and 0.8 v. all versions include an internal power switch and synchronous rect- ifier for minimal external part count and high efficiency. the adp2138/adp2139 have internal soft start and they are internally compensated. during logic controlled shutdown, the input is disconnected from the output and the adp2138/adp2139 draw 0.2 a (typical) from the input source. other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current over- shoot at startup. the adp2138/adp2139 are available in a 6-ball wafer level chip scale package (wlcsp). typical applications circuit on off force pwm a uto vin sw en mode gnd vout adp2138/ adp2139 4.7f 4.7f 2.3v to 5.5v v out 1.0h 0 9496-001 figure 1.
adp2138/adp2139 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 typical applications circuit............................................................ 1 revision history ............................................................................... 2 specifications..................................................................................... 3 input and output capacitor, recommended specifications.. 3 absolute maximum ratings............................................................ 4 thermal resistance ...................................................................... 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 control scheme .......................................................................... 11 pwm mode................................................................................. 11 power save mode........................................................................ 11 enable/shutdown ....................................................................... 11 short-circuit protection............................................................ 12 undervoltage lockout ............................................................... 12 thermal protection.................................................................... 12 soft start ...................................................................................... 12 current limit .............................................................................. 12 100% duty operation................................................................ 12 discharge switch ........................................................................ 12 applications information .............................................................. 13 external component selection ................................................ 13 thermal considerations............................................................ 14 pcb layout guidelines.............................................................. 14 evaluation board ............................................................................ 15 evaluation board layout........................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 4/11rev. 0 to rev. a change to features section ............................................................. 1 added figure 32, renumbered figures sequentially ................ 10 changes to ordering guide .......................................................... 16 1/11revision 0: initial version
adp2138/adp2139 rev. a | page 3 of 16 specifications v in = 3.6 v, v out = 0.8 v ? 3.3 v, t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. all limits at temperature extremes are guaranteed via correlation using standard statistical quality co ntrol (sqc). table 1. parameter test conditions/comments min typ max unit input characteristics input voltage range 2.3 5.5 v undervoltage lockout threshold v in rising 2.3 v v in falling 2.00 2.15 2.25 v output characteristics output voltage accuracy pwm mode ?2 +2 % line regulation v in = 2.3 v to 5.5 v, pwm mode 0.25 %/v load regulation i load = 0 ma ? 800 ma ?0.95 %/a pwm to power save mode current threshold 100 ma input current characteristics dc operating current i load = 0 ma, device not switching 23 30 a shutdown current en = 0 v, t a = t j = ?40c to +85c 0.2 1.0 a sw characteristics sw on resistance pfet 155 240 m nfet 115 200 m current limit pfet switch peak current limit 1100 1500 1650 ma discharge switch (adp2139) 100 enable and mode characteristics input high threshold 1.2 v input low threshold 0.4 v input leakage current en/mode = 0 v (min), 3.6 v (max ) ?1 0 +1 a oscillator frequency 2.6 3.0 3.4 mhz start-up time 250 s thermal characteristics thermal shutdown threshold 150 c thermal shutdown hysteresis 20 c input and output capacitor, recommended specifications t a = ?40c to +125c, unless otherwise specified. all limits at temperature extremes are guaranteed via correlation using standar d statistical quality control (sqc). table 2. parameter symbol min typ max unit minimum input and output capacitance c min 4.7 f capacitor esr r esr 0.001 1
adp2138/adp2139 rev. a | page 4 of 16 absolute maximum ratings table 3. parameter rating vin, en, mode ?0.4 v to +6.5 v vout, sw to gnd ?1.0 v to (v in + 0.2 v) temperature range operating ambient ?40c to +85c operating junction ?40c to +125c storage temperature ?65c to +150c lead temperature range ?65c to +150c soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c esd model human body 1500 v charged device 500 v machine 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. adp2138/adp2139 can be damaged when the junction tempera- ture limits are exceeded. monitoring ambient temperature does not guarantee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. in applications with mod- erate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit for as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in., circuit board. refer to jedec jesd 51-9 for detailed information pertaining to board construction. for additional information, see an-617 applica- tion note, microcsp tm wafer l e vel chip s cale package . jb is the junction-to-board thermal characterization parameter measured in units of c/w. jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than through a single path, which is the procedure for measuring thermal resistance, jb . there- fore, jb thermal paths include convection from the top of the package as well as radiation from the package; factors that make jb more useful in real-world applications than jb . maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) refer to jedec jesd51-8 and jesd51-12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 6-ball wlcsp 170 80 c/w esd caution
adp2138/adp2139 rev. a | page 5 of 16 pin configuration and fu nction descriptions 09496-002 vin en sw gnd vout top view ( ball side down) not to scale 1 2 3 4 5 6 mode figure 2. pin configuration (top view) table 5. pin function descriptions pin no. mnemonic description 1 vin power source input. vin is the source of the pfet high -side switch. bypass vin to gnd with a 4.7 f or greater capacitor as close to the adp2138/adp2139 as possible. 2 sw switch node output. sw is the drain of the p-channe l mosfet switch and n-channel synchronous rectifier. connect the output lc filter between sw and the output voltage. 3 gnd ground. connect the input an d output capacitors to gnd. 4 en buck activation. to turn on the buck, set en to high. to turn off the buck, set en to low. 5 mode mode input. drive the mode pin high for the operating mode to force continuous pwm switching. drive the mode pin low to allow automatic pwm/psm operating mode. 6 vout output voltage sensing input.
adp2138/adp2139 rev. a | page 6 of 16 typical performance characteristics v in = 3.6 v, t a = 25c, v en = v in , unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-003 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 3. efficiency vs. load current, across input voltage, v out = 1.8 v, psm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-004 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 4. efficiency vs. load current, across input voltage, v out = 1.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-005 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 5. efficiency vs. load current, across input voltage, v out = 0.8 v, psm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-006 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 6. efficiency vs. load current, across input voltage, v out = 0.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-007 v in = 3.9v v in = 4.2v v in = 5.5v figure 7. efficiency vs. load current, across input voltage, v out = 3.3 v, psm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 09496-008 v in = 3.9v v in = 4.2v v in = 5.5v figure 8. efficiency vs. load current, across input voltage, v out = 3.3 v, pwm mode
adp2138/adp2139 rev. a | page 7 of 16 1.825 1.815 1.805 1.795 1.785 1.775 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out a (v) 09496-009 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 9. load regulation across input voltage, v out = 1.8 v, pwm mode 0.815 0.810 0.805 0.800 0.795 0.790 0.785 0.780 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out a (v) 09496-010 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v figure 10. load regulation across input voltage, v out = 0.8 v, pwm mode 3.378 3.358 3.318 3.338 3.298 3.278 3.258 3.238 3.218 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out a (v) 09496-011 v in = 3.9v v in = 4.2v v in = 5.5v figure 11. load regulation across input voltage, v out = 3.3 v, pwm mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i out (a) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 frequency (mhz) 09496-012 ?40c +25c +85c +125c figure 12. frequency vs. output current, across temperature, v out = 1.8 v, pwm mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i out (a) 09496-013 v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 frequency (mhz) figure 13. frequency vs. output current, across supply voltage, v out = 1.8 v 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input voltage (v) 90 80 70 60 50 40 30 20 10 0 output voltage (mv) 09496-034 i out = 100a i out = 25ma i out = 500ma figure 14. output voltage ripple vs. input voltage, across output current, v out = 1.8 v
adp2138/adp2139 rev. a | page 8 of 16 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input voltage (v) 350 300 250 200 150 100 50 0 r dson (m ? ) 09496-036 ?40c +25c +125c figure 15. r dson pfet vs. input voltage, across temperature 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input voltage (v) 250 200 150 100 50 0 r dson (m ? ) 09496-037 ?40c +25c +125c figure 16. r dson nfet vs. input voltage, across temperature 09496-014 t 4 4 1 1 2 m 40.0s a ch2 215ma t 2 6 . 0 0 % ch1 100mv ch4 5.00v ch2 250ma ? sw v out i out figure 17. response to load transient, 150 ma to 500 ma, v out = 1.8 v, pwm mode 09496-015 t 4 4 1 1 2 m 40.0s a ch2 215ma t 2 6 . 0 0 % ch1 100mv ch4 5.00v ch2 250ma ? sw v out i out figure 18. response to load transient, 50 ma to 200 ma, v out = 1.8 v, automatic mode 09496-016 t 4 4 1 1 2 m 40.0s a ch2 215ma t 2 6 . 0 0 % ch1 100mv ch4 5.00v ch2 250ma ? sw v out i out figure 19. response to load transient, 150 ma to 500 ma, v out = 0.8 v, pwm mode 09496-017 ch1 100mv ch4 5.00v ch2 100ma ? m 40.0s a ch2 134ma 1 4 t 2 6 . 0 0 % t 1 4 2 sw v out i out figure 20. response to load transient, 50 ma to 200 ma, v out = 0.8 v, automatic mode
adp2138/adp2139 rev. a | page 9 of 16 09496-018 t 4 4 1 1 2 m 40.0s a ch2 275ma t 2 6 . 0 0 % ch1 100mv ch4 5.00v ch2 250ma ? sw v out i out figure 21. response to load transient, 150 ma to 500 ma, v out = 3.3 v, pwm mode 09496-019 t 4 4 1 1 2 m 40.0s a ch2 114ma t 2 6 . 0 0 % ch1 100mv ch4 5.00v ch2 100ma ? sw v out i out figure 22. response to load transient, 50 ma to 200 ma, v out = 3.3 v, automatic mode 09496-020 ch1 20.0mv ch3 1.00v m 40.0s a ch3 4.50v t 1 3 t ?84.0000s v out v in figure 23. response to line transient, v out = 3.3 v, v in = 4.0 v to 4.8 v, pwm mode 09496-021 ch1 20.0mv ch3 1.00v m 40.0s a ch3 4.50v t 1 3 t ?84.0000s v out v in figure 24. response to line transient, v out = 0.8 v, v in = 4.0 v to 4.8 v, pwm mode 09496-033 ch1 20.0mv ch3 1.00v m 40.0s a ch3 4.50v t 1 3 t ?84.0000s v out v in figure 25. response to line transient, v out = 1.8 v, v in = 4.0 v to 4.8 v, pwm mode 09496-022 ch1 2.00v ? ch4 5.00v ch2 500ma ? m 40.0s a ch3 2.50v t 1 0 . 4 0 % ch3 5.00v t 4 1 1 1 3 2 sw v out i in e n figure 26. startup, v out = 1.8 v, i out = 10 ma
adp2138/adp2139 rev. a | page 10 of 16 09496-023 ch1 1.00v ? ch4 5.00v ch2 500ma ? m 40.0s a ch3 2.50v t 1 0 . 4 0 % ch3 5.00v t 4 1 1 1 3 2 sw v out i in e n figure 27. startup, v out = 0.8 v, i out = 10 ma 09496-024 ch1 5.00v ? ch4 5.00v ch2 500ma ? m 40.0s a ch3 2.50v t 1 0 . 4 0 % ch3 5.00v t 4 1 1 1 3 2 sw v out i in e n figure 28. startup, v out = 0.8 v, i out = 10 ma 09496-025 t 4 4 1 1 2 a ch1 3.80mv m 1.00s t 5 0 . 0 0 % ch1 10.0mv ? ch4 2.00v ch2 500ma ? sw v out i l figure 29. typical waveform, v out = 1.8 v, psm mode, i out = 10 ma 09496-026 t 4 1 1 2 a ch4 1.32v m 40.0s t 5 0 . 0 0 % ch1 10.0mv ? ch2 500ma ? ch4 2.00v sw v out i l figure 30. typical waveform, v out = 1.8 v, pwm mode, i out = 200 ma 09496-035 ch1 100mv ch4 2.00v m 40.0s a ch3 1.36v t 2 9 . 6 0 % ch3 2.00v t 4 1 1 1 3 sw mode v out figure 31. mode transition from psm to pwm to psm, v out = 1.8 v 130 120 100 110 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) v out ripple (mv) 09496-100 1.8v, v in = 5.5v, auto 1.8v, v in = 3.6v, auto 1.8v, v in = 2.3v, auto 1.8v, v in = 5.5v, pwm 1.8v, v in = 3.6v, pwm 1.8v, v in = 2.3v, pwm figure 32. v out peak-to-peak ripple vs. output current, v out = 1.8 v
adp2138/adp2139 rev. a | page 11 of 16 theory of operation 09496-027 pwm/ psm control i limit low current psm comp soft start undervoltage lock out thermal shutdown driver and antishoot through oscillator pwm comp gm error amp adp2138 vout mode gnd en sw vin figure 3 3 . adp2138 functional block diagram the adp2138 and adp2139 are step-down dc-to-dc converters that use a fixed frequency and high speed current-mode archi- tecture. the high switching frequency and tiny 6-ball wlcsp package allow for a small step-down dc-to-dc converter solution. the adp2138/adp2139 operate with an input voltage of 2.3 v to 5.5 v, and regulate an output voltage down to 0.8 v. control scheme the adp2138/adp2139 operate with a fixed frequency, current- mode pwm control architecture at medium to high loads for high efficiency, but shift to a power save mode control scheme at light loads to lower the regulation power losses. when operating in pwm mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. when operating in power save mode at light loads, the output voltage is controlled in a hyste- retic manner, with higher v out ripple. during part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. each adp2138/adp2139 has a mode pin, which determines the operation of the buck regulator in either pwm mode (when the mode pin is set high) or power save mode (when the mode pin is set low). pwm mode in pwm mode, the adp2138/adp2139 operate at a fixed frequency of 3 mhz, set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the adp2138/adp2139 regulate the output voltage by adjusting the peak inductor current threshold. power save mode the adp2138/adp2139 smoothly transition to the power save mode of operation when the load current decreases below the power save mode current threshold. when the adp2138 and adp2139 enter power save mode, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level approximately 1.5% above the pwm regulation level, pwm operation turns off. at this point, both power switches are off, and the adp2138/ adp2139 enter into idle mode. c out discharges until v out falls to the pwm regulation voltage, at which point the device drives the inductor to cause v out to rise again to the upper threshold. this process is repeated for as long as the load current is below the power save mode current threshold. power save mode current threshold the power save mode current threshold is set to 100 ma. the adp2138/adp2139 employ a scheme that enables this current to remain accurately controlled, independent of v in and v out levels. this scheme also ensures that there is very little hysteresis between the power save mode current threshold for entry to and exit from the power save mode. the power save mode current threshold is optimized for excellent efficiency across all load currents. enable/shutdown the adp2138/adp2139 start operating with soft start when the en pin is toggled from logic low to logic high. pulling the en pin low forces the device into shutdown mode, reducing the shutdown current to 0.2 a (typical).
adp2138/adp2139 rev. a | page 12 of 16 short-circuit protection the adp2138/adp2139 include frequency fold back to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indi- cating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated on the adp2138/adp2139. if the input voltage drops below the 2.15 v uvlo threshold, the adp2138/adp2139 shut down, and both the power switch and the synchronous rectifier turn off. when the voltage rises above the uvlo threshold, the soft start period is initiated, and the part is enabled. thermal protection in the event that the adp2138/adp2139 junction temperature rises above 150c, the thermal shutdown circuit turns off the converter. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 20c hysteresis is included so that when thermal shutdown occurs, the adp2138/adp2139 do not return to operation until the on-chip temperature drops below 130c. when coming out of thermal shutdown, soft start is initiated. soft start the adp2138/adp2139 have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. after the en pin is driven high, internal circuits begin to power up. start-up time in the adp2138/adp2139 is the measure of when the output is in regulation after the en pin is driven high. start-up time consists of the power-up time and the soft start time. current limit each adp2138/adp2139 has protection circuitry to limit the amount of positive current flowing through the pfet switch and the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a drop in v in or with an increase in i load , the adp2138/ adp2139 reach a limit where, even with the pfet switch on 100% of the time, v out drops below the desired output voltage. at this limit, the adp2138/adp2139 smoothly transition to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the adp2138/adp2139 immediately restart pwm regulation without allowing overshoot on v out . discharge switch the adp2139 has an integrated switched resistor (of typically 100 ) to discharge the output capacitor when the en pin goes low or when the device enters undervoltage lockout or thermal shutdown. the time to discharge is typically 200 s. 09496-028 pwm/ psm control i limit low current psm comp soft start under-voltage lock out thermal shutdown driver and antishoot through oscillator pwm comp gm error amp adp2139 vout mode gnd en sw vin figure 3 4 . adp2139 functional block diagram
adp2138/adp2139 rev. a | page 13 of 16 applications information external component selection trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in figure 1 . inductor the high switching frequency of the adp2138/adp2139 allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. recommended inductors are shown in tabl e 6 . the peak-to-peak inductor current ripple is calculated using the following equation: lfv vvv i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 )( ripple max load peak i ii + = inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dcr. larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the adp2138/adp2139 are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low electromagnetic interference (emi). table 6. suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 lqm18pn1r0 1.6 0.8 0.33 700 52 taiyo yuden cbmf1608t1r0m 1.6 0.8 0.8 290 90 epl2014-102ml 2.0 2.0 1.4 900 59 coilcraft tdk glfr1608t1r0m-lr 1.6 0.8 0.8 360 80 0603ls-102 1.8 1.27 1.1 400 81 coilcraft toko mdt2520-cn 2.5 2.0 1.2 1800 100 output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu- lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 4.0466 f at 1.8 v, as shown in figure 3 5 . substituting these values in the equation yields c eff = 4.0466 f (1 ? 0.15) (1 ? 0.1) = 3.0956 f to guarantee the performance of the adp2138/adp2139, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 6 5 4 3 2 1 0 012345 dc bias voltage (v) capacitance (f) 09496-029 6 figure 3 5 . typical capacitor performance the peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: () out sw in ripple clf v v = 2 2 out sw ripple cf i = 8 capacit ors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr
adp2138/adp2139 rev. a | page 14 of 16 the effective capacitance needed for stability, which includes temperature and dc bias effects, is 3 f. table 7. suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 coilcraft tdk x5r c1608x5r0j475 0603 6.3 input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v vvv ii )( )( ? to minimize supply noise, place the input capacitor as close to the vin pin of the adp2138/adp2139 as possible. as with the output capacitor, a low esr capacitor is recommended. the list of recommended capacitors is shown in table 8 . table 8. suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 coilcraft tdk x5r c1608x5r0j475 0603 6.3 thermal considerations because of the high efficiency of the adp2138/adp2139, only a small amount of power is dissipated inside the adp2138/adp2139 package, which reduces thermal constraints. however, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junc- tion temperature of 125c. if the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers when the junction temperature falls below 130c. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation: t j = t a + t r where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to power dissipation. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package. p d is the power dissipation in the package. pcb layout guidelines poor layout can affect adp2138/adp2139 performance, causing emi and electromagnetic compatibility problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. to implement a good layout, use the following rules: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the com- ponent side ground to further reduce noise interference on sensitive circuit nodes.
adp2138/adp2139 rev. a | page 15 of 16 evaluation board vin tb1 tb3 tb4 tb2 tb6 t5 22 1 6 1 3 4 5 en vin vout gnd out gnd in en mode vin gnd sw en mode vout cout 4.7f cin 4.7f l1 1h 09496-030 u1 figure 3 6 . evaluation board schematic evaluation board layout 09496-031 figure 3 7 . top layer 09496-032 figure 3 8 . bottom layer
adp2138/adp2139 rev. a | page 16 of 16 outline dimensions 12-07-2010-a a b c 0.640 0.595 0.550 0.370 0.355 0.340 0.270 0.240 0.210 1.070 1.030 0.990 1.545 1.505 1.465 12 bottom view (ball side up) top view (ball side down) side view 0.340 0.320 0.300 1.00 ref 0.50 ref ball a1 identifier seating plane 0.50 ref coplanarity 0.05 figure 3 9 . 6-ball wafer level chip scale package [wlcsp] (cb-6-12) dime nsions sho wn in millimeters ordering guide model 1 temperature range output voltage (v) package description package option branding adp2138acbz-0.8-r7 ?40c to +125c 0.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 ljh adp2138acbz-1.0-r7 ?40c to +125c 1.0 6-ball wafer level chip scale package [wlcsp] cb-6-12 l88 adp2138acbz-1.2-r7 ?40c to +125c 1.2 6-ball wafer level chip scale package [wlcsp] cb-6-12 l89 adp2138acbz-1.5-r7 ?40c to +125c 1.5 6-ball wafer level chip scale package [wlcsp] cb-6-12 l8a adp2138acbz-1.8-r7 ?40c to +125c 1.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 l8c adp2138acbz-2.5-r7 ?40c to +125c 2.5 6-ball wafer level chip scale package [wlcsp] cb-6-12 l93 adp2138acbz-2.8-r7 ?40c to +125c 2.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 ldh adp2138acbz-3.0-r7 ?40c to +125c 3.0 6-ball wafer level chip scale package [wlcsp] cb-6-12 ldj adp2138acbz-3.3-r7 ?40c to +125c 3.3 6-ball wafer level chip scale package [wlcsp] cb-6-12 ldp adp2139acbz-0.8-r7 ?40c to +125c 0.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 ljj adp2139acbz-1.0-r7 ?40c to +125c 1.0 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhn adp2139acbz-1.2-r7 ?40c to +125c 1.2 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhp adp2139acbz-1.5-r7 ?40c to +125c 1.5 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhq adp2139acbz-1.8-r7 ?40c to +125c 1.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhr adp2139acbz-2.5-r7 ?40c to +125c 2.5 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhs adp2139acbz-2.8-r7 ?40c to +125c 2.8 6-ball wafer level chip scale package [wlcsp] cb-6-12 lht adp2139acbz-3.0-r7 ?40c to +125c 3.0 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhu adp2139acbz-3.3-r7 ?40c to +125c 3.3 6-ball wafer level chip scale package [wlcsp] cb-6-12 lhv 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09496-0-4/11(a)

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